Embodiments relate to a semiconductor device and a method for forming the same, and more particularly to a semiconductor device including a vertical gate.
As the integration degree of a semiconductor device is increased, a channel length of a transistor is gradually decreased. However, the reduction in channel length of the transistor may result in a Drain Induced Barrier Lowering (DIBL) phenomenon, a hot carrier effect, and a short channel effect such as punch-through. In order to address such issues, a variety of methods are being intensively researched by many developers and companies, for example, a method for reducing a depth of a junction region, a method for relatively increasing a channel length by forming a recess in a channel region of a transistor, and the like.
However, the integration density of a semiconductor memory device (especially, Dynamic Random Access Memory (DRAM)) has come close to Gigabits, it is necessary to manufacture a smaller-sized transistor. Therefore, under a structure using a current planar transistor in which a gate electrode is formed over a semiconductor substrate and a junction region is formed at both sides of the gate electrode, it is difficult to satisfy a required unit cell size. In order to solve the above-mentioned problems, a vertical channel transistor structure is recently proposed. However, a vertical-channel transistor structure may utilize a complicated fabrication process. Specifically, the vertical-channel transistor has a difficulty in forming a buried bit line at a lower portion of a word line, such that it is hard to mass-production. In addition, as a unit cell of the semiconductor device is gradually reduced in size, there is a need to improve performance (or throughput) of a circuit formed in the peripheral region.